Product specifications
The CS2600 is a system-clocking device incorporating a programmable phase-locked loop (PLL). The hybrid analog/ digital PLL architecture comprises a delta-sigma fractional-N analog PLL and a digital frequency-locked loop (FLL). The CS2600 enables frequency synthesis and clock generation from a stable timing reference clock. The device can generate low-jitter clocks from a noisy clock reference at frequencies as low as 150 Hz. An internal oscillator can provide the timing reference clock, enabling a reduction in external component requirements. The CS2600 can be configured using a control interface supporting I2C and SPI modes of operation. The device can also be configured in Hardware Control Mode using pull-up/pull-down resistors, reducing system software overhead.
The CS2600 supports BCLK and FSYNC outputs, derived from the PLL output signal. All of the clock outputs can be phase-aligned with the clock input source. The automatic rate control (ARC) function detects the clock input frequency and configures the PLL ratio for the required output. The ARC supports seamless transitions through changes in the reference frequency; the BCLK and FSYNC outputs are automatically adjusted to maintain the applicable ratios.
The CS2600 provides a built-in OTP memory to configure the default operating settings, loaded at boot-up. The OTP memory is optimized and managed to support multiple programming cycles. The CS2600 can be powered from a single 1.8 V or 3.3 V supply. The device combines high performance with low power consumption.
The CS2600 is available in commercial-grade 16-pin QFN package for operation from –40°C to +85°C. The device is also available in the AEC-Q100-qualified grade-2 package for operation from –40°C to +105°C.
Features
• High-performance analog/digital phase locked loop
• Clock frequency synthesizer incorporating delta-sigma fractional-N analog PLL
o Generates low-jitter 6–75 MHz clock (CLK_OUT) from 8–75 MHz timing reference (REF_CLK_IN)
• Fractional clock multiplier and jitter reduction using hybrid analog/digital PLL
o Generates low-jitter 6–75 MHz clock (CLK_OUT), synchronized to a 150 Hz–30 MHz low-quality or intermittent frequency reference (CLK_IN)
• Flexible timing reference source
o External clock or external crystal
• Great performance
o High resolution PLL ratio (1 PPM)
o 18 psRMS period jitter
o 18 psRMS period jitter with internal reference
• Glitchless clock output generated from intermittent input
• BCLK and FSYNC outputs (derived from CLK_OUT) for digital audio applications
o Phase alignment with CLK_IN frequency reference
• Automatic rate control (ARC) for digital audio applications
o Seamless transitions through changes in CLK_IN frequency reference
• Customer-programmable startup configuration, using integrated one-time programmable (OTP) memory
• Hardware and software control modes
o I2C/SPI control port
o Hardware control with no host processor required
• Configurable auxiliary clock/status output
• Minimal board space required
o No external analog loop-filter components
• Single-supply operation at 1.8 V or 3.3 V
