Product specifications
The CS2501 is a system-clocking device incorporating a programmable phase-locked loop (PLL). The hybrid analog/ digital PLL architecture comprises a delta-sigma fractional-N analog PLL and a digital frequency-locked loop (FLL). The CS2501 enables clock generation from a stable timing reference clock. The device can generate low-jitter clocks from a noisy clock reference at frequencies as low as 50 Hz. An internal oscillator can provide the timing reference clock, enabling a reduction in external component requirements.
The CS2501 can be configured using a control interface supporting I2C and SPI modes of operation. The CS2501 can be powered from a single 1.8 V or 3.3 V supply. The device combines high performance with low power consumption.
The CS2501 is available in commercial-grade 10-pin TSSOP package for operation from –40°C to +85°C. The device is also available in the AEC-Q100-qualified grade-2 package for operation from –40°C to +105°C.
Features
• High-performance analog/digital phase locked loop
• Fractional clock multiplier and jitter reduction using hybrid analog/digital PLL
o Generates low-jitter 6–75 MHz clock (CLK_OUT), synchronized to a 50 Hz–30 MHz low-quality or intermittent frequency reference (CLK_IN)
• Flexible timing reference source
o External clock, external crystal or built-in oscillator
• Great performance
o High resolution PLL ratio (1 PPM)
o 18 psRMS period jitter
o 18 psRMS period jitter with internal reference
• Glitchless clock output generated from intermittent input
• I2C/SPI control port
• Configurable auxiliary clock/status output
• Minimal board space required
o No external analog loop-filter components
• Pin-to-pin, register map, and control compatible with CS2100 and CS2300
• Single-supply operation at 1.8 V or 3.3 V
